Trench device isolation

专利摘要:
Disclosed is a trench device isolation method of a semiconductor device capable of preventing dishing by keeping the width of an inactive region the same. To this end, the present invention comprises the steps of laminating a pad oxide film and a material layer on a semiconductor substrate, patterning the resultant material layer is laminated to remove a portion of the material layer and to laminate the first insulating film, Laminating a second insulating film on the entire surface of the semiconductor substrate on which the insulating film is formed and etched back so that it remains only in the region where the material layer is removed, the first insulating layer and the material layer below the second insulating layer as an etching mask Etching a portion of the semiconductor substrate to form a trench; depositing a third insulating layer on the entire surface of the semiconductor substrate on which the trench is formed; and exposing the surface of the semiconductor substrate on a resultant product on which the second insulating layer is formed. It provides a trench device isolation method of a semiconductor device comprising the step of proceeding to a planarization process until.
公开号:KR19980056118A
申请号:KR1019960075382
申请日:1996-12-28
公开日:1998-09-25
发明作者:김병철
申请人:김광호；삼성전자 주식회사；
IPC主号:

专利说明:

Trench device isolation
The present invention relates to a trench device isolation method of a semiconductor device of the present invention, and more particularly, to a trench device isolation method of a semiconductor device capable of preventing dishing by maintaining the same width of an inactive region.
While the trend toward higher integration of semiconductor devices is making the semiconductor devices lighter and shorter, there are many difficulties in the process of manufacturing such semiconductor devices. In particular, the reduction of design rules in the process limits the manufacturing process of semiconductor devices in sub-micron units. As a result, the process margin of each unit process is greatly reduced. For example, a change is urgently required in the device isolation process for electrical isolation between devices. Conventional device isolation methods for memory devices of 256 megabits or less have used a local oxidation of silicon (LOCOS) process. However, when the conventional LOCOS process is used for a memory device of 1 gigabit or more, The bird's beak phenomenon not only narrows the active area, but also greatly reduces the electrical insulation capability. In addition, when the planarization is not properly achieved may result in poor patterning in the subsequent process. For this reason, a trench device isolation method, in which a portion of a semiconductor substrate is etched into a trench to fill an insulator, is widely used in a large-capacity memory device process.
1 to 5 are cross-sectional views illustrating a trench device isolation method according to the prior art.
FIG. 1 shows that when the pad oxide film 3 is formed on the semiconductor substrate 1 with a thickness of 100 to 300 GPa, and the nitride film 5 is deposited on the pad oxide film 3 to a thickness of 1000 to 2500 GPa. It is a cross section.
FIG. 2 is a cross-sectional view when a photoresist is applied to the entire surface of the nitride film on which the nitride film is deposited, and a portion of the nitride film 5 and the pad oxide film 3 below is removed by performing a photo and etching process.
3 is a cross-sectional view when the trench 7 is formed by removing the photoresist and performing anisotropic etching on the lower semiconductor substrate using the nitride film 5 as an etching mask.
FIG. 4 is a cross-sectional view when an insulating film 9 such as Tetra Ethyl Ortho Silicate (O3-TEOS) is stacked on the front surface of the resultant trench to form a trench 7 in the front surface of the semiconductor substrate.
FIG. 5 illustrates an etching back or chemical mechanical polishing (CMP) process on the entire surface of the semiconductor substrate on which the second insulating film 9 is formed. It is sectional drawing when the pad oxide film 3 is removed and planarization is completed and the trench element isolation process of a semiconductor device is completed.
The problem in the above-mentioned prior art is that the first problem is the biggest problem, because the depth of the trench varies according to the change in the width of the inactive area, and thus the plate shape is formed in the inactive area after the CMP process. The dishing of 11 may be caused. For this reason, the element isolation capability is lowered, and the flatness is deteriorated at the time of subsequent gate electrode formation, resulting in pattern defects. In addition, since the sharp step 13 is formed at the edge of the trench region, a problem arises that the leakage current of the gate oxide film is caused to weaken the overall transistor characteristics due to the hump phenomenon.
An object of the present invention is to provide a trench device isolation method of a semiconductor device capable of preventing dishing by maintaining the same width of an inactive region.
1 to 5 are cross-sectional views illustrating a trench device isolation method according to the prior art.
6 to 11 are cross-sectional views illustrating a trench device isolation method of a semiconductor device in accordance with a preferred embodiment of the present invention.
* Description of Major Symbols in Drawings *
100: semiconductor substrate, 102: pad oxide film,
104: material layer, 106: first insulating film,
108: second insulating film, 110: trench,
112: third insulating film.
In order to achieve the above technical problem, the present invention, the step of laminating the pad oxide film and the material layer on the semiconductor substrate, by patterning the resultant material layer is laminated to remove a portion of the material layer and the first insulating film laminated Stacking a second insulating film on the entire surface of the semiconductor substrate on which the first insulating film is formed and etching back so that the second insulating layer remains only in the region where the material layer is removed; Etching a portion of the insulating layer, the material layer, and the semiconductor substrate to form a trench; depositing a third insulating layer on the entire surface of the semiconductor substrate on which the trench is formed; And a planarization process until the surface of the semiconductor substrate is exposed to provide the trench device isolation method of the semiconductor device.
According to the present invention, it is possible to realize a trench device isolation method of a semiconductor device capable of preventing dishing by maintaining the same width of an inactive region.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
6 to 11 are cross-sectional views illustrating a trench device isolation method of a semiconductor device in accordance with a preferred embodiment of the present invention.
Referring to FIG. 6, a pad oxide film 102 is formed on the surface of the semiconductor substrate 100 to a thickness of 100 to 300 GPa, and a material layer 104 such as polysilicon is sequentially deposited to a thickness of 1000 to 2500 GPa.
Referring to FIG. 7, a photoresist film is coated on the entire surface of the resultant material layer 104 on which the material layer 104 is formed, and a portion of the lower material layer 104 is patterned by performing a photo and etching process. A first insulating film 106, for example, a nitride film, is deposited on the entire surface of the continuously patterned semiconductor substrate to a thickness of 500 to 2000 GPa.
Referring to FIG. 8, the second insulating film 108 is deposited on the entire surface of the resultant in which the first insulating film 106 is deposited by using an insulating film such as Tetra Ethyl Ortho Silicate (O3-TEOS) and etchback. As a result, the second insulating layer 108 remains only in a region where only a part of the material layer is removed.
Referring to FIG. 9, after etching the lower nitride film 106 using the second insulating film 108 as an etch mask, the trench 110 may be anisotropically etched on the lower semiconductor substrate to form an inactive region. To form. In this case, as the material layer 5 made of polysilicon is etched together, the pad oxide layer 102 becomes an end point of the etching.
Here, the method of etching the nitride film and the semiconductor substrate using the second insulating film 108 as an etching mask is an important means for achieving the object of the present invention. This is because the width of the inactive region can be kept constant as the second insulating layer acts as an etching mask, thereby effectively preventing dishing caused by a subsequent CMP process. In addition, the gate electrode continuous to the device isolation process may be formed while the second insulating film 108 remains or is removed from the semiconductor substrate, or may be formed while the pad oxide film 102 remains.
Referring to FIG. 10, a trench may be filled by forming a third insulating layer 112 to have a sufficient thickness of about 2000 to about 5000 microns using an insulating material such as O3-TEOS on the entire surface of the resultant in which the trench 110 is formed. Proceed with the process so that
Referring to FIG. 11, an etch back or CMP process is performed on the entire surface of the resultant product on which the second insulating film 112 is formed, and thus the pad oxide film 102, the nitride film 106, and the second film are present on the semiconductor substrate 100. The insulating film 108 and the third insulating film are removed to complete the device isolation process of the entire semiconductor device.
The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.
Therefore, according to the present invention described above, by forming an trench using an insulating film such as O3-TEOS as an etching mask, the trench element of the semiconductor device that can prevent the dishing phenomenon by maintaining the same width of the inactive region A separation method can be implemented.

权利要求:
Claims (1)
[1" claim-type="Currently amended] Stacking a pad oxide film and a material layer on a semiconductor substrate;
Patterning the resultant material on which the material layer is stacked to remove a part of the material layer and stacking a first insulating layer;
Stacking a second insulating film on an entire surface of the semiconductor substrate on which the first insulating film is formed, and etching back the second insulating film so that the material layer remains only in a region where the material layer is removed;
Etching the lower portion of the first insulating layer, the material layer, and the semiconductor substrate using the second insulating layer as an etch mask to form a trench;
Stacking a third insulating layer on an entire surface of the semiconductor substrate on which the trench is formed;
And performing a planarization process until the surface of the semiconductor substrate is exposed on the resultant material on which the second insulating layer is formed.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-28|Application filed by 김광호, 삼성전자 주식회사

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1996-12-28|Priority to KR1019960075382A

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1998-09-25|Publication of KR19980056118A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960075382A|KR19980056118A|1996-12-28|1996-12-28|Trench device isolation|